1. Field of the Invention
The present invention generally relates to an automatic logic synthesis technique for automatizing logic circuit design and, more particularly, to a logic circuit generator for generating highly testable logic circuits.
2. Description of the Prior Art
In a typical logic circuit generator, testability of a logic circuit generated thereby is not usually considered a priority. Accordingly, it often becomes necessary to correct the logic circuit having been generated in order to improve the testability thereof.
Shown in FIG. 19 is a flow chart illustrating a logic circuit design method using the typical conventional logic circuit generator.
In step 41 a test circuit is inserted to a logic circuit generated by the logic circuit generator or designed manually. Typically, a test circuit so called "scan path" is inserted therein. This step is performed manually by an operator or automatically by a computer. In step 42, formation of test vectors is performed by analyzing the logic circuit wherein the test circuit has been inserted. This step is also performed manually by a circuit designer using test vectors provided for logical check or automatically by the computer. In step 43, a fault simulation is executed for the logic circuit using test vectors formed in step 42 to obtain a fault detection rate. The fault detection rate is evaluated to determine if it is sufficiently high or not in step 44. If it is evaluated sufficiently high, the test design is completed. If it is not, the flow returns to the step 42 for formation of test vectors to add a further test vector, or to the step 41 for test circuit insertion to correct the logic circuit.
Shown in FIG. 20 is a block diagram of a first example of the conventional logic circuit generator in which testability is taken into consideration. In the figure, reference numeral 51 denotes a logic synthesizing means for synthesizing a logic circuit satisfying given functions according to a functional description about a logic circuit input beforehand; 52 denotes a scan-path inserting means for inserting a scan path to a logic circuit synthesized by the logic synthesizing means 51 for testing; and 53 denotes a circuit optimizing means for eliminating redundancy of the logic circuit generated from the insertion of the scan path.
In the scan-path inserting means 52, flip-flops contained in a logic circuit are replaced with scan-path use flip-flops having the function of shift registers and the flip-flops are sequentially connected into one scan path. Also, a scan data I/O port and a scan-use clock input port are inserted thereinto. It is known that the logic circuit into which a scan path is thus inserted can be easily tested by setting data into or reading data from the flip-flops through the scan path in testing.
Shown in FIG. 21 is a block diagram of a second example of the conventional logic circuit generator in which testability is taken into consideration. In the figure, a reference numeral 61 denotes a function-level testability analyzing means for analyzing the testability of a circuit in a functional level according to a functional description about a logic circuit input beforehand; 62 denotes a function-level scan-path inserting means for modifying the original functional description so as to include a scan path, if necessary, according to results of analysis obtained; and 63 denotes a logic synthesizing means for synthesizing a logic circuit from the functional description to which a scan path is thus added.
The logic circuit generated by the conventional logic circuit generator as described above includes a scan path as in the first example of the counterpart, whereby it is easy to test. Moreover, it has a scan path that is inserted thereinto only when required, according to results of analysis regarding the testability in a function level, thus affording an advantage that the resulting test circuit requires only low cost as compared with the first conventional counterpart.
Although it is necessary to take the testability of a logic circuit into consideration upon forming the functional description thereof in order to obtain a logic circuit having a high testability using the conventional logic circuit generator (wherein the testability is not taken into consideration), there is no guarantee that a high ratio of fault detection is obtained according to this method since it is difficult to exactly estimate the testability of a logic circuit to be generated in a functional level.
In the method for inserting a test circuit into the logic circuit generated according to the test design flow shown in FIG. 19, it is difficult for the designer to correct the logic circuit. Further, there are some problems that redundancy is generated in the logic circuit after conversion, and restrictions in the design which were satisfied before conversion are not satisfied after conversion, due to an automatic replacement that takes only the testability into consideration in those cases where the test circuit is automatically inserted by the computer.
In the first example of the conventional logic circuit generator shown in FIG. 20, in which testability is taken into consideration, the testability of a synthesized logic circuit is not analyzed. Therefore, all the flip-flops must be replaced with scan-path use ones, causing the cost for generated logic circuits to be increased to a great extent.
In the second example of the conventional logic circuit generator shown in FIG. 21, in which testability is taken into consideration, the testability is evaluated in not logic level but function level. However, since accurate testability analysis of the generated logic circuit is difficult in the function level, it may cause an insufficiently high fault detection ratio, or an increase in cost since the test circuit will be excessively large.